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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Fast Throughput Rate: 3MSPS Specified for VDD of 2.35 V to 3.6V Low Power: 13.5 mW max at 3MSPS with 3V Supplies Wide Input Bandwidth: 70dB SNR at 1MHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Power Down Mode: 1A max 8-Lead TSOT Package 8-Lead MSOP Package APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors
3MSPS,10-/12-Bit ADCs in 8-Lead TSOT AD7273/AD7274
FUNCTIONAL BLOCK DIAGRAM
V DD
GND
V IN V REF
T/H
10-/12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK
CONTROL LOGIC
SDATA
&6
AD7273/AD7274
GND
GENERAL DESCRIPTION The AD7273/AD7274 are 10-bit and 12-bit, high speed, low power, successive-approximation ADCs respectively. The parts operate from a single 2.35V to 3.6 V power supply and feature throughput rates up to 3 MSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of TBD MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. The conversion rate is determined by the SCLK. There are no pipeline delays associated with the part. The AD7273/AD7274 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is applied externally and can be in the range of 1.2V to VDD. This allows the widest dynamic input range to the ADC.
PRODUCT HIGHLIGHTS 1. 3MSPS ADCs in an 8-lead TSOT package. 2. High Throughput with Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The AD7273/ AD7274 features a power down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 A max when in Power Down mode. 4. Reference can be driven up to the power supply. 5. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered tradermarks are the property of their respective companies.
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2004
PRELIMINARY TECHNICAL DATA
AD7273-SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth Power Supply Rejection Ratio (PSRR) DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error 2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Range DC leakage Current Input Capacitance Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate
NOTES 1 Temperature range from -40C to +85C. 2 See Terminology. 3 Guaranteed by Characterization. Specifications subject to change without notice.
(VDD=+2.35 V to +3.6 V, VREF= +2.5V , fSCLK=52 MHz, fSAMPLE=3 MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
B Grade1 61 -73 -74 -82 -82 TBD TBD TBD TBD TBD 10 0.5 0.5 1 TBD 1 TBD TBD 0 to VREF 0.5 TBD 1.2 to VDD TBD TBD TBD 0.7(V DD ) 2 0.2(V DD ) 0.8 0.5 TBD 10 Units dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ dB typ Bits LSB LSB LSB LSB LSB LSB LSB fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz Test Conditions/Comments fIN = 1 MHz Sine Wave
@ 3 dB @ 0.1dB
max max max typ max typ max
Guaranteed No Missed Codes to 10 Bits
Volts A max pF typ Vmin/Vmax A max pF max k typ V min V min V max V max A max A max pF max 2.35V Vdd 2.7V 2.7V< Vdd 3.6V 2.35V Vdd< 2.7V 2.7V Vdd 3.6V Typically TBD nA, VIN= 0 V or VDD
VDD - 0.2 V min 0.2 V max 1 A max 10 pF max Straight (Natural) Binary 230 50 3 ns max ns max MSPS max
ISOURCE= 200 A,VDD= 2.35 V to 3.6 V I SINK = 200A
12 SCLK cycles with SCLK at 52 MHz
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PRELIMINARY TECHNICAL DATA
AD7273-SPECIFICATIONS
Parameter POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down
NOTES 1 Temperature range from -40C to +85C. 2 See Terminology. 3 Guaranteed by Characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice.
(VDD=+2.35 V to +3.6 V, VREF= +2 .5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
B Grade1 2.35/3.6 2.5 4.5 1 TBD Units V min/Vmax mA mA A mA typ max max typ Digital I/Ps= 0V or VDD VDD= 2.35V to 3.6V, SCLK On or Off VDD= 2.35V to 3.6V, f SAMPLE = 3MSPS SCLK On or Off, typically TBD nA V DD= 3V, f SAMPLE = 1MSPS V DD = 3 V , fSAMPLE = 3MSPS V DD = 3 V Test Conditions/Comments
13.5 3
mW max W max
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PRELIMINARY TECHNICAL DATA
AD7274-SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Term Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth Power Supply Rejection Ratio (PSRR) DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Offset Error2 Gain Error 2 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Range DC leakage Current Input Capacitance Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN,SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 2 Throughput Rate
NOTES 1 Temperature range from -40C to +85C. 2 See Terminology. 3 Guranteed by Characterization. Specifications subject to change without notice.
(VDD=+2.35 V to +3.6 V, VREF= +2.5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
B Grade1 70 71 -80 -82 -84 -84 TBD TBD TBD TBD TBD 12 1 1 TBD TBD TBD 0 to VREF 0.5 TBD dB dB dB dB Units min min typ typ fa= TBD kHz, fb= TBD kHz fa= TBD kHz, fb= TBD kHz Test Conditions/Comments fIN = 1 MHz Sine Wave
dB typ dB typ ns typ ps typ MHz typ MHz typ dB typ Bits LSB LSB LSB LSB LSB
@ 3 dB @ 0.1dB
max max Guaranteed No Missed Codes to 12 Bits max max max
Volts A max pF typ
1.2 to VDD Vmin/Vmax TBD A max TBD pF max TBD k typ 0.7(VDD) 2 0.2(VDD) 0.8 0.5 TBD 10 V min V min V max V max A max A max pF max 2.35V Vdd 2.7V 2.7V < Vdd 3.6V 2.35V Vdd< 2.7V 2.7V Vdd 3.6V Typically TBD nA, VIN= 0 V or VDD
VDD - 0.2 V min ISOURCE= 200 A;VDD= 2.35 V to 3.6 V 0.2 V max I SINK=200 A 1 A max 10 pF max Straight (Natural) Binary 270 50 3 ns max 14 SCLK Cycles with SCLK at 52 MHz ns max MSPS max See Serial Interface Section
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PRELIMINARY TECHNICAL DATA
AD7274 SPECIFICATIONS
Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode(Static) Full Power-Down Mode(Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down
(VDD=+2.35 V to +3.6 V, VREF= + 2.5V, fSCLK=52 MHz, fSAMPLE=3MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
B Grade1 2.35/3.6 2.5 4.5 1 TBD Units V min/Vmax mA typ mA max A max mA typ Digital I/Ps= 0V or VDD VDD= 2.35V to 3.6V,SCLK On or Off V DD= 2.35V to 3.6V, f SAMPLE=3MSPS SCLK On or Off, typically TBD nA VDD= 3V, fSAMPLE=1MSPS Test Conditions/Comments
13.5 3
mW max VDD= 3 V, fSAMPLE= 3MSPS W max VDD= 3 V
NOTES 1 Temperature range from -40C to +85C. 2 See Terminology. 3 Guranteed by Characterization. 4 See Power Versus Throughput Rate section. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7273/AD7274 TIMING SPECIFICATIONS1
Parameter f SCLK
2
Preliminary Technical Data
(VDD= +2.35 V to +3.6 V; VREF = 2.5V, TA= TMIN to TMAX, unless otherwise noted.)
Units KHz min 3 MHz max AD7274 AD7273 Description
Limit at TMIN, TMAX AD7273/AD7274 20 52 14 x tSCLK 12 x tSCLK TBD 10 TBD TBD TBD 0.4t SCLK 0.4t SCLK TBD TBD TBD TBD
t CONVERT
t QUIET t1 t2 t 34 t 44 t5 t6 t 74 t 85 t power-up 6
ns min ns ns ns ns ns ns ns ns ns s min min max max min min min max min max
Minimum Quiet Time required between Bus Relinquish and start of Next Conversion Minimum CS Pulse Width CS to SCLK Setup Time Delay from CS Until SDATA Three-State Disabled Data Access Time After SCLK Falling Edge SCLK Low Pulse Width SCLK High Pulse Width SCLK to Data Valid Hold Time SCLK Falling Edge to SDATA Three-State SCLK Falling Edge to SDATA Three-State Power Up Time from Full Power-down
NOTES 1 Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of VDD) and timed from a voltage level of 1.6Volts. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum f sclk at which specifications are guaranteed. 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage. 5 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See Power-up Time section. Specifications subject to change without notice.
200A
I OL
t7 SCLK
TO OUTPUT PIN CL 25pF 200A +1.6V
SDATA
IOH
V IH V IL
Figure 1. Load Circuit for Digital Output Timing Specifications
Figure 3. Hold time after SCLK falling edge
t4 SCLK
t8 SCLK
SDATA
SDATA
V IH V IL
1.6 V
Figure 2. Access time after SCLK falling edge
Figure 4. SCLK falling edge to SDATA Three-State
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
Figures 5 and 6 show some of the timing parameters from the Timing Specifications table.
t1
AD7273/AD7274
&6
tconvert t2
SCLK 1 2 3 4
t6
5 13
B
14 15 16
t3
SDATA THREESTATE Z ZERO DB11 DB10
t7 t4
DB9 DB1 DB0
t5
ZERO
t8
ZERO
tquiet
THREE-STATE
2 LEADING ZERO'S 1/ THROUGHPUT
2 TRAILING ZERO'S
Figure 5. AD7274 Serial Interface Timing Diagram
Timing Example 1 From Figure 6, having fSCLK = 52 MHz and a throughput of 3MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. Figure 6 shows that, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a value of TBD ns for tQUIET satisfying the minimum requirement of TBD ns. Timing Example 2 Having fSCLK = 20 MHz and a throughput of 1.5 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 666 ns. With t2 = TBD ns min, this leaves tACQ to be TBD ns. This TBD ns satisfies the requirement of 50 ns for tACQ. From Figure 6, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = TBD ns max. This allows a values of TBD ns for tQUIET satisfying the minimum requirement of TBD ns.
t1
&6
tconvert t2
SCLK 1 2 3 4 5 12 13
B
14 15 16
t8
tquiet
12.5(1/fSCLK) 1/THROUGHPUT
tacquisition
Figure 6. Serial Interface Timing Example
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
Preliminary Technical Data
8-lead MSOP Package JA Thermal Impedance.................................205.9C/W JC Thermal Impedance...............................43.74C/W Lead Temperature Soldering Reflow (10-30 secs)....................................+TBDC ESD..................................................................TBDKV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
V DD to GND......................................-0.3 V to TBD V Analog Input Voltage to GND......-0.3 V to VDD + 0.3 V Reference Input Voltage to GND...-0.3 V to VDD + 0.3 V Digital Input Voltage to GND..............-0.3 V to TBD V Digital Output Voltage to GND....-0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2..........10 mA Operating Temperature Range Commercial (B Grade)......................-40C to +85C Storage Temperature Range..............-65C to +150C Junction Temperature..........................................150C 8-lead TSOT Package JA Thermal Impedance.................................TBDC/W JC Thermal Impedance................................TBDC/W
PIN CONFIGURATION AD7273/AD7274
VDD SDATA
1 2 3 4
8
V IN GND SCLK VREF
VDD SDATA GND VIN
1 2 3 4
8
GND
&6
GND
AD7273/ AD7274 TOP VIEW
(Not to Scale)
7 6 5
AD7273/ AD7274 TOP VIEW
(Not to Scale)
7 6 5
&6
SCLK VREF
8-lead MSOP
8-lead TSOT
ORDERING GUIDE
Model AD7274BUJ-REEL AD7274BRM AD7273BUJ-REEL AD7273BRM
Temperature Range -40C -40C -40C -40C to to to to +85C +85C +85C +85C
Linearity Error (LSB)1 1 max 1 max 0.5 max 0.5 max
Package Option UJ-8 RM-8 UJ-8 RM-8
Package Description TSOT MSOP TSOT MSOP
Branding Information TBD TBD TBD TBD
NOTES 1 Linearity error here refers to integral nonlinearity.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7273/AD7274 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
PIN FUNCTION DESCRIPTION
AD7273/AD7274
Pin Mnemonic CS V DD GND VIN V REF
Function Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7273/AD7274 and also frames the serial data transfer. Power Supply Input. The VDD range for the AD7273/AD7274 is from +2.35V to +3.6V. Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 to VREF. Voltage Reference Input. This pin becomes the reference voltage input and an external reference should be applied at this pin. The external reference input range is 1.2V to VDD. A TBD F capacitor should be tied between this pin and AGND. Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7274 consists of two leading zeros followed by the 12 bits of conversion data followed by two trailing zeros, which is provided MSB first. The data stream from the AD7273 consists of two leading zeros followed by the 10 bits of conversion data followed by four trailing zeros, which is provided MSB first. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7273/AD7274's conversion process.
SDATA
SCLK
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
TERMINOLOGY Integral Nonlinearity (INL)
Preliminary Technical Data
Total Harmonic Distortion (THD)
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7273/AD7274, the endpoints of the transfer function are zero scale, a 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity (DNL)
Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. It is defined as:
V2 + V3 + V 4 + V5 + V 6 V1
2 2 2 2 2
THD (dB ) = 20 log
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4 , V5 and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e, AGND + 0.5 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e, VREF - 1.5LSB after the offset error has been adjusted out.
Total Unadjusted Error (TUE)
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion (IMD)
This is a comprehensive specification which includes gain, linearity and offset errors.
Track/Hold Acquisition Time
The Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 0.5 LSB, after the end of conversion. See Serial Interface section for more details.
Signal to Noise Ratio (SNR)
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7273/AD7274 are tested using the CCIF standard where two input frequencies are used (see fa and fb in the specification page). In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
Power Supply Rejection Ratio (PSRR)
This is the measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwitdh (fs/2). The rms value of a sine wave is one half its peak to peak value divided by 2 and the rms value for the quantization noise is q/12. The ratio is dependant on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as:
SNR = 6.02 N + 1.76 dB
Thus for a 12-bit converter this is 74 dB, for a 10-bit converter it is 62 dB. Practically, though, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal AC noise sources, etc.
Signal-to- (Noise + Distortion) Ratio (SINAD)
The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency fs.
PSRR (dB) = 10 log (Pf/ Pfs)
Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs coupled onto the ADC VDD supply.
Aperture Delay
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms value of the sine wave and noise is the rms sum of all nonfundamentals signals up to half the sampling frequency (fs/2), including harmonics but excluding dc.
This is the measured interval between the leading edge of the sampling clock and the point at which the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in time at which the sample is taken.
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
CIRCUIT INFORMATION
AD7273/AD7274
When the ADC starts a conversion, see Figure 8, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code. Figure 9 shows the ADC transfer function.
The AD7273/AD7274 are high speed, low power, 10-/12Bit, single supply, analog-to-digital converters (ADC) respectively. The parts can be operated from a +2.35V to +3.6V supply. When operated from any supply voltage within this range, the AD7273/AD7274 are capable of throughput rates of 3 MSPS when provided with a 52 MHz clock. The AD7273/AD7274 provide the user with an on-chip track/hold, A/D converter, and a serial interface housed in an 8-lead TSOT or an 8-lead MSOP package, which offers the user considerable space saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for the successive-approximation A/D converter. The analog input range is 0 to VREF. An external reference is required by the ADC and this reference can be in the range of 1.2V to VDD. The AD7273/AD7274 also feature a Power-Down option to allow power saving between conversions. The power down feature is implemented across the standard serial interface as described in the Modes of Operation section.
CONVERTER OPERATION
CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR CONTROL LOGIC
A V IN SW1 B
SW2
CONVERSION PHASE
COMPARATOR
V DD / 2
AGND
Figure 8. ADC Conversion Phase
The AD7273/AD7274 is a successive-approximation analog-to-digital converter based around a charge redistribution DAC. Figures 7 and 8 show simplified schematics of the ADC. Figure 7 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the com-
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight binary. The designed code transitions occur midway between succesive integer LSB values, i.e, 0.5LSB, 1.5LSBs, etc. The LSB size is VREF/4096 for the AD7274, VREF/1024 for the AD7273. The ideal transfer characteristic for the AD7273/AD7274 is shown in Figure 9.
CHA R GE RE DI ST R I B UT I ON DAC SA MP LI NG CAP AC I TOR CON T RO L LO GI C
A VI N SW1 B
111...111 111...110
ADC CODE
1LSB = VREF /4096 (AD7274) 1LSB = V REF /1024 (AD7273)
ACQUI SI TI ON PH AS E
SW2
111...000 011...111
COMPA R AT OR AG N D V DD / 2
Figure 7. ADC Acquisition Phase
000...010 000...001 000...000 0V
0.5LSB +V DD -1.5LSB
ANALOG INPUT
Figure 9. AD7273/AD7274 Transfer Characteristic
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
PERFORMANCE CURVES Dynamic Performance curves TPC 1 and TPC 2 show typical FFT plots for the AD7274 and AD7273 respectively, at 3 MSPS sample rate and TBD KHz input tone. TPC 3 shows the Signal-to-(Noise+Distortion) Ratio performance versus Input frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7274. TPC 4 shows the Signal to Noise Ratio (SNR) performance versus Input frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7274. TPC 5 shows a graph of the Total Harmonic Distortion (THD) versus Analog input signal frequency for various supply voltages while sampling at 3 MSPS with a SCLK frequency of 52 MHz for the AD7274. TPC 6 shows a graph of the Total Harmonic Distortion (THD) versus Analog input frequency for different source impedances when using a supply voltage of TBD V, SCLK frequency of 52 MHz and sampling at a rate of 3 MSPS for the AD7274. See Analog Input section. TPC 7 shows the Power Supply Rejection Ratio (PSRR) versus Supply Ripple Frequency for the AD7274 when no decoupling is used. See PSRR in the Terminology section. DC Accuracy curves TPC 8and TPC 9 show typical INL and DNL performance for the AD7276. TP10 and TPC11 show Change in DNL and INL versus Reference Voltage when using a supply voltage of 3V. Power Requirements curves TPC12 shows Maximum current versus Supply voltage for the AD7274 with different SCLK frequencies. See also Power versus Throughput Rate.
Preliminary Technical Data
Typical Performance Characteristics
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TPC 1. AD7274 Dynamic performance at 3 MSPS
TPC 2. AD7273 Dynamic performance at 3 MSPS
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data AD7273/AD7274
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TPC 3. AD7274 SINAD vs Analog Input Frequency at 3 MSPS for various Supply Voltages
TPC 6. THD vs. Analog Input Frequency for various Source Impedance
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TPC 4. AD7274 SNR vs Analog Input Frequency at 3 MSPS for various Supply Voltages
TPC 7. Power Supply Rejection Ratio (PSRR) versus Supply Ripple Frequency
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TPC 5. THD vs. Analog Input Frequency at 3 MSPS for various Supply Voltages
TPC 8. AD7276 INL performance
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PRELIMINARY TECHNICAL DATA AD7273/AD7274 Preliminary Technical Data
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TPC 9. AD7276 DNL performance
TPC 12. Maximum current vs Supply voltage for different SCLK frequencies.
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TPC 10. Change in INL versus Reference Voltage
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TPC 11. Change in DNL versus Reference Voltage
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
TYPICAL CONNECTION DIAGRAM
AD7273/AD7274
Voltage Reference AD780@2.5V REF192 ADR421 ADR291 AD7274 SNR Performance TBD kHz Input TBD TBD TBD TBD dB dB dB dB
Figure 10 shows a typical connection diagram for the AD7273/AD7274. An external reference must be applied to the ADC. This reference can be in the range of 1.2V to VDD. A precision reference like the REF19X family or the ADR421 can be used to supply the reference voltage to the AD7273/AD7274. The conversion result is output in a 16-bit word with two leading zeros followed by the 12-bit or 10-bit result. The 12-bit result from the AD7274 will be followed by two trailing zeros and the 10-bit result from the AD7273 will be followed by four trailing zeros. Table I provides some typical performance data with various references under the same set-up conditions.
Table I. AD7274 performance for various Voltage References IC
0.1F TBD mA 0V toVREF INPUT +2.5V REF192 VREF 10F +3.6V SUPPLY
VIN
VDD
AD7274/ AD7273
SCLK SDATA DSP/ C/P
1F 0.1F
TANT
GND
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SERIAL INTERFACE
Figure 10. AD7273/AD7274 Typical Connection Diagram
Analog Input
Figure 11 shows an equivalent circuit of the analog input structure of the AD7273/AD7274. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10mA is the maximum current these diodes can conduct without causing irreversable damage to the part. The capacitor C1 in Figure 11 is typically about 4pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about TBD. The capacitor C2 is the ADC sampling capacitor and has a capacitance of TBD pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of a bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op-amp will be a function of the particular application.
VDD
D1 C2 TBD PF R1 VIN
C1 4pF
D2 CONVERSION PHASE - SWITCH OPEN TRACK PHASE - SWITCH CLOSED
Figure 11. Equivalent Analog Input Circuit
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
Table II provides some typical performance data with various op-amps used as the input buffer under the same set-up conditions. Op-amp in the input buffer AD8510 AD8610 AD8038 AD8519 AD7274 SNR Performance TBD kHz Input TBD dB TBD dB TBD dB TBD dB
Preliminary Technical Data
MODES OF OPERATION
Table II. AD7274 performance for various Input Buffers
The mode of operation of the AD7273/AD7274 is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, Normal Mode and Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated will determine whether the AD7273/ AD7274 will enter Power-Down Mode or not. Similarly, if already in Power-Down then CS can control whether the device will return to Normal operation or remain in Power-Down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/ throughput rate ratio for different application requirements.
Normal Mode
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. See TPC6.
Digital Inputs
This mode is intended for fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7273/AD7274 remaining fully powered all the time. Figure 12 shows the general diagram of the operation of the AD7273/AD7274 in this mode. The conversion is iniated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling, the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. For the AD7274 a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7273 a minimum of 12 serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again.
The digital inputs applied to the AD7273/AD7274 are not limited by the maximum ratings which limit the analog inputs. Instead, the digitals inputs applied can go to TBD V and are not restricted by the VDD + 0.3V limit as on the analog inputs. For example, if the AD7273/AD7274 were operated with a VDD of 3V then 5V logic levels could be used on the digital inputs. However, it is important to note that the data output on SDATA will still have 3V logic levels when VDD= 3V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3V limit is the fact that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3V was applied prior to VDD.
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SCLK
1 10 12 14 16
AD7273/74
SDATA
VALID DATA
Figure 12. Normal Mode Operation
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
Power-Down Mode
AD7273/AD7274
In order to exit this mode of operation and power the AD7273/AD7274 up again, a dummy conversion is performed. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up once 16 SCLKs have elapsed and valid data will result from the next conversion as shown in Figure 14. If CS is brought high before the 10th falling edge of SCLK, then the AD7273/AD7274 will go back into Power- Down again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So, although the device may begin to power up on the falling edge of CS, it will power down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.
This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7273/AD7274 is in Power-Down, all analog circuitry is powered down. To enter Power-Down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 13. Once CS has been brought high in this window of SCLKs, then the part will enter Power-Down and the conversion that was intiated by the falling edge of CS will be terminated and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, then the part will remain in Normal Mode and will not power-down. This will avoid accidental power-down due to glitches on the CS line.
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SCLK
1
2
10
16
SDATA
INVALID DATA
THREE-STATE
Figure 13. Entering Power Down Mode
THE PART BEGINS TO POWER UP
THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED
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SCLK
A
1
10
16
1
16
SDATA
INVALID DATA
VALID DATA
Figure 14. Exiting Power Down Mode
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
Power-up Time
Preliminary Technical Data
This means, assuming one has the facility to monitor the ADC supply current, if the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track.
POWER VERSUS THROUGHPUT RATE
The power-up time of the AD7273/AD7274 is TBD ns, which means that with any frequency of SCLK up to 52 MHz, one dummy cycle will always be sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quite time tQUIET must still be allowed from the point where the bus goes back into three-state after the dummy conversion, to the next falling edge of CS. When running at 3 MSPS throughput rate, the AD7273/AD7274 will power up and acquire a signal within 0.5 LSB in one dummy cycle, i.e. TBD ns. When powering up from the Power-Down mode with a dummy cycle, as in Figure 14, the track and hold which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as point A in Figure 14. Although at any SCLK frequency one dummy cycle is sufficient to power the device up and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; TBD ns will be sufficient to power the device up and acquire the input signal. If, for example, a 25 MHz SCLK frequency was applied to the ADC, the cycle time would be 640 ns. In one dummy cycle, 640 ns, the part would be powered up and VIN acquired fully. However after TBD ns with a 25 MHz SCLK only TBD SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case the CS can be brought high after the 10th SCLK falling edge and brought low again after a time tQUIET to initiate the conversion. When power supplies are first applied to the AD7273/ AD7274, the ADC may either power up in the PowerDown mode or in Normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the Power-Down mode while not in use and the user wishes the part to power up in Power-Down mode, then the dummy cycle may be used to ensure the device is in Power-Down by executing a cycle such as that shown in Figure 13. Once supplies are applied to the AD7273/AD7274, the power up time is the same as that when powering up from the Power-Down mode. It takes approximately TBD ns to power up fully if the part powers up in Normal mode. It is not necessary to wait TBD ns before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the PowerDown mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track and hold will already be in track.
By using the Power-Down mode on the AD7273/AD7274 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 15 shows how as the throughput rate is reduced, the device remains in its Power-Down state longer and the average power consumption over time drops accordingly. For example, if the AD7273/AD7274 is operated in a continuous sampling mode with a throughput rate of 500KSPS and a SCLK of 52MHz (VDD= 3V), and the device is placed in the Power-Down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 13.5 mW (VDD= 3V). If the power up time is one dummy cycle, i.e. 333ns, and the remaining conversion time is another cycle, i.e. 333ns, then the AD7273/AD7274 can be said to dissipate 13.5mW for 666ns during each conversion cycle.If the throughput rate is 500KSPS, the cycle time is 2s and the average power dissipated during each cycle is (666/2000) x (13.5 mW)= 4.5mW. Figure 15 shows the Power vs. Throughput Rate when using the Power-Down mode between conversions at 3V. The Power-Down mode is intended for use with throughput rates of approximately TBD MSPS and under as at higher sampling rates there is no power saving made by using the Power-Down mode.
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Figure 15. Power vs Throughput
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PRELIMINARY TECHNICAL DATA Preliminary Technical Data
SERIAL INTERFACE
AD7273/AD7274
return to three-state on the 16th SCLK falling edge, as shown in Figure 17. If the user considers a 14 SCLKs cycle serial interface for the AD7273/AD7274, CS needs to be brought high after the 14th SCLK falling edge, the last two trailing zeros will be ignored and SDATA will go back into three-state. In this case, a 45 MHz serial clock would allow to achieve 3MSPS throughput rate. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the 2nd leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge. In that case, the first falling edge of SCLK will clock out the second leading zero and it could be read in the first rising edge. However, the first leading zero that was clocked out when CS went low will be missed unless it was not read in the first falling edge. The 15th falling edge of SCLK will clock out the last bit and it could be read in the 15th rising SCLK edge. If CS goes low just after one the SCLK falling edge has elapsed, CS will clock out the first leading zero as before and it may be read in the SCLK rising edge. The next SCLK falling edge will clock out the second leading zero and it could be read in the following rising edge.
t1
Figures 16 and 17 show the detailed timing diagram for serial interfacing to the AD7274 and AD7273 respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7273/AD7274 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. The conversion is also initiated at this point. For the AD7274 the conversion will require 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed the track and hold will go back into track on the next SCLK rising edge as shown in Figure 16 at point B. If the rising edge of CS occurs before 14 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state. If 16 SCLKs are considered in the cycle, the last two bits will be zeros and SDATA will return to three-state on the 16th SCLK falling edge as shown in Figure 16. For the AD7273 the conversion will require 12 SCLK cycles to complete. Once 11 SCLK falling edges have elapsed, the track and hold will go back into track on the next SCLK rising edge, as shown in Figure 17 at point B. If the rising edge of CS occurs before 12 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state. If 16 SCLKs are considered in the cycle, the AD7273 will clock out four trailing zeros for the last four bits and SDATA will
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tconvert t2
SCLK 1 2 3 4
t6
5 13
B
14 15 16
t3
SDATA THREESTATE Z ZERO DB11 DB10
t7 t4
DB9 DB1 DB0
t5
ZERO
t8
ZERO
tquiet
THREE-STATE
2 LEADING ZERO'S 1/ THROUGHPUT
2 TRAILING ZERO 'S
Figure 16. AD7274 Serial Interface Timing Diagram
t1
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tconvert t2
SCLK 1 2 3 4 10 11
B
12
t6
13 14 15 16
t3
SDATA THREESTATE Z ZERO DB9
t4
DB8
t5
DB1 DB0 ZERO
t7
ZERO ZERO
t8
ZERO
tquiet
THREE-STATE
2 LEADI NG ZERO'S 1/ THROUGHPUT
4TRAILING ZERO'S
Figure 17. AD7273 Serial Interface Timing Diagram
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PRELIMINARY TECHNICAL DATA AD7273/AD7274
OUTLINE DIMENSIONS
Dimensions shown in millimiters
Preliminary Technical Data
8-Lead Thin Small Outline Transistor Package [TSOT] (UJ- 8)
2 .90 BSC
PR00001-0-6/04(PrB)
8
7
6
5
1 .6 0 BSC
1 2 3 4
2 .8 0 BSC
PIN 1 0 .6 5 BSC 0 .9 0 0 .8 7 0 .8 4 1.9 5 BSC
1 .00 MAX 0 .38 0 .22
0 .2 0 0 .0 8 8 4 0
0 .1 0 MAX
SEATING PLANE
0 .5 5 0 .4 5 0 .3 5
COMPLIANT TO JEDEC STANDARDS MO-193BA
8-Lead Mini Small Outline Package [MSOP] (RM - 8)
3.0 0 BSC
8
5
3 .00 BSC
1 4
4.9 0 BSC
PIN 1 0 .6 5 BSC 0 .1 5 0 .0 0 0 .3 8 0 .2 2 COPLANARITY 0 .10 SEATING PLANE 1 .1 0 MAX 8 0 0 .80 0 .60 0 .40
0 .2 3 0 .0 8
COMPLIANT TO JEDEC STANDARDS MO-187AA
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